Monday, April 17, 2006
Power estimation technology donated to Accelera
Atrenta has donated its SpyGlass Design Constraints for low power design to Accellera's Unified Power Format Technical Subcommittee.
Atrenta has donated its SpyGlass Design Constraints (SGDC) for low power design to Accellera's Unified Power Format (UPF) Technical Subcommittee. Atrenta's constraint format enables IC designers to specify design intent for voltage domains and power isolation domains. The format also supports advanced low power techniques at various phases of the design, including RTL, post-synthesis and post-routing.
Atrenta's SpyGlass-Low Power solution has been widely adopted across state-of-the-art production design flows.
Using SpyGlass Low Power, customers can verify that design implementation is aligned with low power design intent.
Atrenta's power estimation technology enables customers to gauge power consumption at RTL to within 20% of silicon-measured power.
Additional capabilities help customers optimise the design for power efficiency, cutting IC power consumption by up to 40%.
'Atrenta's customers will benefit immensely from a low power standard that simplifies low power design', said Dr Ajoy Bose, Chairman, President and CEO of Atrenta.
'At the end of the day, standards are all about customer productivity, which is why we are actively participating in all viable standards initiatives'.
Atrenta has donated its SpyGlass Design Constraints (SGDC) for low power design to Accellera's Unified Power Format (UPF) Technical Subcommittee. Atrenta's constraint format enables IC designers to specify design intent for voltage domains and power isolation domains. The format also supports advanced low power techniques at various phases of the design, including RTL, post-synthesis and post-routing.
Atrenta's SpyGlass-Low Power solution has been widely adopted across state-of-the-art production design flows.
Using SpyGlass Low Power, customers can verify that design implementation is aligned with low power design intent.
Atrenta's power estimation technology enables customers to gauge power consumption at RTL to within 20% of silicon-measured power.
Additional capabilities help customers optimise the design for power efficiency, cutting IC power consumption by up to 40%.
'Atrenta's customers will benefit immensely from a low power standard that simplifies low power design', said Dr Ajoy Bose, Chairman, President and CEO of Atrenta.
'At the end of the day, standards are all about customer productivity, which is why we are actively participating in all viable standards initiatives'.
# posted by Swathi @ 11:15 AM 
