Saturday, November 25, 2006

 

Power inductors have low profiles

Multilayer power inductors are made for high switching frequencies.

TDK has announced the availability of the company's first multilayer power inductors for high switching frequencies. The MLP2520, MLP3225 and MLP3216 feature excellent DC/AC resistance, which results in improved efficiency and standby time, both of which are paramount for battery driven devices. Thanks to their multilayer design, the inductors have a low profile of approximately 1mm, making them ideal for handheld applications.

TDK has designed these products for use as DC/DC convertors in small devices.

The company recognised the need for engineers to reduce the size of their devices, so it turned to its extensive experience in multilayer technology to develop these lower profile power inductors.

The design of the MLP2520, MLP3225, and MLP3216 power inductors make them well suited for small devices such as mobile phones, PDAs, and portable MP3 players.

Furthermore, the ferrite materials used to construct these power inductors are bespoke for this product type.

The inductors also boast excellent mounting strength thanks to SMD chip making.

The components are RoHS compliant and completely lead-free.

The MLP3225, MLP3216 and the MLP2520 are available in three standard heights, with case sizes of 3.2 x 2.5, 3.2 x 1.6 and 2.5 x 2.0mm, respectively.

The MLP2520 has a height of 1mm and resistance of 0.06-0.11ohm, and current ratings of 1100-1500mA.

The MLP3216 has a height of 0.8mm and resistance of 0.12-0.13ohm, and current rating of 1000mA.

 

Group gains unified front across Europe

Europe-wide rebrand creates better synergy between Abacus Group distribution businesses across Europe and provides platform for continued development and growth.

Abacus Group has announced the establishment of a clear and distinctive corporate identity throughout Europe. This Europe-wide rebrand has been implemented to create a better synergy between the group's distribution businesses across Europe and to provide a stronger platform for continued development and growth. The rebranding exercise involved renaming many of Abacus Group's businesses in Europe, and new distinctive yet consistent logos for all its operations.

Abacus Group Chief Executive, Martin Kent, said: 'Our recent acquisitions moved Abacus into the top five component distribution companies in Europe, and we now need to promote the name of Abacus everywhere'.

'I believe very strongly that people buy from people, but increasingly they also buy from scale'.

'A pervasive brand name can add to an excellent business with great local relationships'.

Most Abacus Group Electronic Component Distribution (ECD) companies will now have Abacus as part of their company name.

Abacus Group's three specialist distribution businesses, and the remaining ECD businesses will retain their existing names, but receive a new logo that includes part of the Abacus symbol as a unifying graphic element.

All businesses will be identified as Abacus Group companies on their business stationery and promotional materials.

In the UK, Deltron will be renamed Abacus Deltron and Abacus Polar becomes simply Abacus.

Micromark C and CD becomes just Micromark, and Trident and TDC retain their existing names.

All businesses will adopt a new logo in line with the Group identity.

In Germany, Austria, France and the Netherlands, former Deltron companies have been renamed Abacus Deltron, and in Italy the Group's two businesses are being combined as Abacus ECC.

Axess Technology in France will retain its existing name, but receives a new unified logo and RDI becomes Abacus RDI.

In the Scandinavian region the Deltron and Promax names will be dropped, and the businesses will trade as Abacus.

The exception to this is Deltron Conelec in Denmark, which becomes Conelec and adopts a new style logo.

Friday, November 24, 2006

 

Boundary scan interface links design to production

Goepel Electronic has introduced a new graphical user interface (GUI) for its System Cascon boundary scan software platform.

Goepel Electronic has introduced a new graphical user interface (GUI) for its System Cascon boundary scan software platform. The new user interface features an innovative Multi-Phase-Inspector, supporting all product life cycle stages, from the comprehensive management of design data and boundary scan applications in the lab, to new product introduction (NPI) in the manufacturing environment, manufacturing process test (MPT), fault analysis at repair stations, and field service applications, all within a completely integrated software environment. 'With the introduction of the Multi-Phase-Inspector, our worldwide established boundary scan software System Cascon is arguably the best product among the advanced boundary scan tools available today, providing superior ease of use and offering the highest level of automation', says Heiko Ehrenberg, Manager of US Operations at Goepel Electronics in Austin, Texas.

'New or occasional users will appreciate the user-friendliness, while frequent and expert users are benefiting especially from the significantly increased productivity in System Cascon'.

'At the same time, this strategically important innovation is the basis for the consequent implementation of our philosophy of extended boundary scan'.

At the Multi-Phase-Inspector's core, three work spaces - Design Inspector, Application Inspector and Production Inspector - guide the user through the various project phases.

Within a selected work space, various tasks and actions are logically arranged as individual branches in a tree structure.

Selecting a particular branch provides access to the tools, files, options, and reports linked to the task at hand.

Currently, System Cascon includes 30 integrated tools, linked intelligently to each other.

Such an integrated development environment results in a very high transparency of underlying processes, allowing the user to quickly solve problems with the help of interactive analysis tools.

Auto-scripting and auto-generation features can be used to automatically generate the intelligent unit under test (UUT) database and any test and in-system programming (ISP) applications in automated process batches, further enhancing the test system's productivity.

Design changes or bill of material variations, for example, can easily be accommodated with user controlled auto-scripting by automatically processing all project data and re-generating all test and ISP applications.

Development times for ISP of Flash and PLD as well as all kinds of boundary scan test procedures are significantly shortened compared with conventional, nonintegrated solutions.

With the myCascon feature, System Cascon manages various users' individual projects, automatically initialising project files and settings from the previous session when the user is logging in again.

Such operating system functions are beneficial not only for the individual user, but support the management of concurrent engineering throughout a company.

System Cascon is the only boundary scan software on the market that is completely scalable through an integrated licence manager.

Desired software configurations for development stations, programming stations, test stations, debug and repair stations, or service stations can be customised with enable codes, supporting both node-locked licence and floating licence arrangements.

This approach also allows temporary reconfigurations and supports third party integrations, implemented through the Cascon application programming interface (CAPI).

 

Ultracapacitor modules deliver up to 1500V

Compact, fully integrated 125V Boostcap ultracapacitor module provides an easy-to-integrate building block for scalable energy storage and power delivery solutions for electric vehicles.

Maxwell Technologies has introduced a compact, fully integrated 125V Boostcap ultracapacitor module to provide an easy-to-integrate building block for scalable energy storage and power delivery solutions for heavy hybrid and electric vehicles and heavy duty industrial applications requiring up to 1500V. Dr Richard Balanson, Maxwell's President and Chief Executive Officer, said that the new HTM BMOD0063-P125 module is based on 2.7V Boostcap MC3000 power cells and incorporates proprietary balancing, monitoring and thermal management capabilities to ensure industry-leading charge/discharge performance, high reliability and long operational life. 'This high-performance module is designed specifically to satisfy rapidly growing global demand for ultracapacitor-based braking energy recuperation and torque assist systems for hybrid bus and truck drive trains and electric rail vehicles', Balanson said.

'It meets or exceeds transportation industry requirements for watt-hours of energy storage and watts of power delivery per kilogram, and is designed to perform reliably through one million or more deep charge/discharge cycles, which equates to more than 15 years of operational life'.

Michael Everett, Maxwell's Vice President and Chief Technical Officer, said that integrated monitoring capabilities and a highly efficient cooling configuration enable the new module to sustain continuous current of up to 150A with minimal temperature increase in high-temperature environments.

'In addition to managing high current, this module is built to withstand the harsh environments and extremely demanding duty cycles that are typical with heavy transportation applications', Everett said.

'Proprietary design refinements and material science also are significantly reducing manufacturing cost, positioning Maxwell to compete favourably with other energy storage alternatives'.

The HTM BMOD0063-125 is encased in a rugged, splash-proof, IP65-compliant, aluminium chassis, weighs less than 50kg and measures 315 x 425 x 744mm.

Up to 12 modules may be linked in series to deliver a total of us much as 1500V.

Maxwell also offers a complete line of standard 15 to 48V multicell packs and modules, and recently announced a 'quick-turn' programme that offers shipment within 14 days of receipt of a customer purchase order for custom-configured modules for applications requiring up to 540V.

Thursday, November 23, 2006

 

Middleware enables US Navy computing environment

OpenFusion RTOrb Java Edition CORBA middleware has been selected by Raytheon for development and deployment in the US Navy's DDG 1000 Zumwalt Class Destroyer programme.

PrismTech has announced that its OpenFusion RTOrb Java Edition CORBA middleware has been selected by Raytheon for development and deployment in the US Navy's DDG 1000 Zumwalt Class Destroyer programme. Formerly known as the DD(X) destroyer programme, DDG 1000 Zumwalt is the lead ship of a class of next-generation multi-mission destroyers tailored for land attack and littoral dominance. DDG 1000 will provide forward presence and deterrence, and operate as an integral part of joint and combined expeditionary forces.

Raytheon serves as the prime mission systems equipment integrator for the DDG 1000 programme.

PrismTech's OpenFusion RTOrb Java Edition CORBA middleware provides a unified COTS-based solution for integrating diverse distributed systems.

Raytheon will incorporate OpenFusion RTOrb Java Edition in its implementation of the Total Ship Computing Environment Infrastructure (TSCEI - an integrated suite of standardised, open architecture hardware, operating system, middleware and infrastructure services.

Developed for the US Navy by Raytheon and its subcontractors, TSCEI forms the backbone of the Navy's Total Ship Computing Environment - a robust, enterprise-network computing system on which all DDG 1000 application software programs run.

'We're excited to bring PrismTech's real time middleware technology to the DDG 1000 programme', stated Ed Geisler, Vice President and DDG 1000 Programme Manager for Raytheon Integrated Defense Systems.

'Selection of PrismTech is a great example of how DDG 1000 is executing the Navy's Open Architecture (OA) strategy'.

'From a technical perspective, DDG 1000 uses a modular architecture that is based on open standards'.

'The RTOrb product fits well with that architecture'.

Geisler continued: 'OA isn't just about technical solutions'.

'It's also about an open business model that features competition'.

'The selection of PrismTech came through a process which uses formal evaluation criteria and a source selection board to ensure that the Navy gets the best value'.

'There are several products in this technology space and it was determined that the offering from PrismTech, a privately held company, provides the best value to the Navy'.

PrismTech's feature-rich OpenFusion RTOrb Java Edition CORBA middleware provides crucial real-time and non-real-time functionality, PrismTech's offering is based on open industry standards governed by the Object Management Group (OMG) and features a high degree of interoperability with other mission systems middleware used in the DDG 1000 architecture.

'PrismTech offers unparalleled levels of functionality and flexibility for TSCEI implementations', said Steve Jennis, Senior Vice President of Corporate Development at PrismTech.

'Within a single ORB solution, we can meet the wide variety of CORBA and Java technology needs - hard and soft real time - that these demanding infrastructure environments are now requiring'.

The significance of offering deterministic operation in a distributed environment can not be over emphasised, explained Jennis.

'It provides the vehicle for CORBA applications written in the Java programming language to realise more predictable performance with little, and in some cases no, change to the existing code'.

 

Java machine hosts application distribution

Aonix and ProSyst Software have joined forces to provide a Java-based service platform that can be remotely managed.

Aonix, a provider of complete solutions for safety- and mission-critical applications, and ProSyst Software, a leading provider of OSGi-compliant software to embedded Java developers have joined forces to provide a Java-based service platform that can be remotely managed. This framework addresses growing distributed computing complexities in the real-time market by creating a common platform architecture to ensure that all software involved in an application communicates consistently and effectively. The companies have signed an agreement paving the way to jointly market and sell the ProSyst mBedded Server and Aonix PERC technologies.

The products provide an environment especially effective in applications with resource-constrained dynamic network devices such as those used in smart phones, infotainment and telematics systems, and remote monitoring and diagnosis of trains and fleet vehicles.

ProSyst's mBedded Server implements the OSGi Core and Service Compendium specifications on top of virtual machines, such as Aonix PERC.

The product is organised into functional bundle packages, with the OSGi framework serving as the main package of mBedded Server.

The package provides a comprehensive, modular and scalable Java-based software that enables the deployment, maintenance, and removal of applications and their components across different types of devices.

Other features include the reusability of divided applications, common logic exchange through shared components and libraries, and certified compliancy with the OSGi Service Platform Release 4.0.

Aonix PERC Ultra has been successfully tested with the mBedded Server and has proven to be a predictable and reliable source to deploy OSGi applications.

Together, the two products offer compelling value in the form of addon OSGi bundles designed to suit the needs of large commercial customers.

Aonix and ProSyst are working together to establish a reference implementation for prototyping activities that will appeal to the automotive industry, created on a PowerPC-based development platform containing user-selectable RTOS environments.

Both companies are currently involved in joint customer activities including a large US auto manufacturer and microprocessor supplier.

'Our OSGi solutions are used in many different environments, such as automotive telematics systems, residential gateways and mobile devices', noted Kai Hackbarth, Product Manager at ProSyst.

'Aonix PERC Ultra is a reliable, efficient virtual machine and provides the excellent execution platform that our customers seek'.

'Used together, Aonix PERC Ultra and ProSyst mBedded Server provide a powerful combination that enables device and car manufacturers, service providers and service developers to build more complex and dynamic applications while reducing development and maintenance cost'.

'Today's applications continue to become more complex and distributed', noted Gary Cato, Strategic Alliances Manager at Aonix.

'A communications framework based on emerging industry standards reduces that complexity and assures fast and effective interactions between widely dispersed devices'.

'The OSGi framework implemented in the ProSyst mBedded Server powered by the Aonix PERC Ultra virtual machine provides a tremendous advantage to companies implementing distributed Java-based applications'.

PERC Ultra is available for Linux, Windows, and Solaris hosts and supports a wide variety of processor architectures and real-time operating systems.

PERC development tools are available at no charge.

Wednesday, November 22, 2006

 

Simulator expands high-frequency capabilities

Nexxim v3.5 is the latest version of Ansoft's high-performance circuit simulator.

Nexxim v3.5 is the latest version of Ansoft's high-performance circuit simulator. Nexxim v3.5 continues its emphasis on simulation speed, capacity and accuracy, while introducing new analyses and Verilog A support, further enhancing the simulation of high-performance electronic design, from signal integrity analysis to high-frequency ICs used in communications systems. Building on the software architecture and success of the previous releases, Nexxim v3.5 introduces oscillator, circuit envelope, periodic transfer function, Monte-Carlo and load-pull analyses to its transient, harmonic balance and noise (time variant and phase) simulation capabilities.

Additionally, Nexxim v3.5 natively supports Verilog A, which adds a new dimension of design simulation by enabling system descriptions other than electrical.

'Our latest enhancements to Nexxim are critical to the full characterisation of multigigabit computer and communication backplanes as well as RFICs', said Dr Mark Reichelt, Director of Product Development.

'The additional analyses, such as oscillator analysis and circuit envelope, address the autonomous source and digitally modulated circuits found specifically in communication ICs, while other capabilities, such as convolution, state-space methods and model caching, provide an efficient method for handling the larger frequency-based models that are finding their way into time-based signal integrity analysis'.

Nexxim v3.5 is available on PCs running Microsoft Windows 2000 and XP, Sun Solaris and Linux.

 

Wireless SoC reference flow bears fruit

Cadence Design Systems and UMC have announced the success of their RF integrated-circuit design and verification on a codeveloped wireless system-on-chip (SoC) reference flow.

Cadence Design Systems and leading global semiconductor foundry UMC have announced the success of their RF integrated-circuit design and verification on a codeveloped wireless system-on-chip (SoC) reference flow. The flow, featuring the Cadence QRC Extraction and the Virtuoso UltraSim Full-chip Simulator, combines the Cadence Virtuoso custom design platform and UMC's RFCMOS process to deliver silicon-accurate chip simulation and verification flows. UMC and Cadence announced their alliance to streamline wireless design for the fabless market on 6th October 2005.

Since then, UMC has successfully produced a test chip that verifies the Cadence QRC Extraction technology.

The Cadence Virtuoso UltraSim provided UMC with transistor-level transceiver simulation, which reduced the verification cycle time by half.

UMC and Cadence worked closely together to develop a methodology and flow to verify post-layout transistor-level full-chip transceivers, by combining UMC's 0.13um MM/RF PDK validated for the Virtuoso platform, silicon-accurate Cadence QRC Extraction technology, and the Virtuoso UltraSim.

'Designers building SoCs for wireless applications can gain a competitive advantage when they use Virtuoso combined with UMC's RFCMOS process', said Patrick Lin, Chief SoC Architect at UMC.

'For back annotation verification, Cadence QRC Extraction provides a convenient and accurate methodology to predict the performance in critical building blocks such as LC-tank VCO.

Further, the extraction that covers RLCK can be used to predict with greater accuracy the frequencies and how the design will perform in silicon'.

'These benefits and our alliance with Cadence have resulted in a seamless design environment for the analogue/RF design communities'.

The continually increasing demand for feature-rich wireless devices with complex functionality and minimised area and power requirements is driving the need for silicon-accurate parasitic extraction and transistor-level full-chip simulation flows that reduce risk and time to market for custom wireless SoCs.

'Cadence and UMC are working side-by-side to drive and deliver integrated, low-cost, high-performance, low-power wireless SoC solutions to our mutual customers', said Charles Giorgetti, Corporate Vice-President, Product Marketing, at Cadence.

'By collaborating with UMC, we are able to provide a silicon-validated methodology that meets changing requirements for wireless designers as they develop new and increasingly more innovative products'.

Tuesday, November 21, 2006

 

Marcisz leads US sales offensive

Solido Design Automation has opened its US sales and support office and has appointed Zdzislaw 'Z' Marcisz as Sales Director.

Solido Design Automation has opened its US sales and support office and has appointed Zdzislaw 'Z' Marcisz as Sales Director. Marcisz will be responsible for the management of sales and field operations and will oversee the day-to-day operations of Solido's new location in the San Francisco Bay Area. 'We are pleased to offer sales and support resources in the USA and we look forward to harnessing Z's expertise in the EDA industry and knowledge of major accounts to support Solido's growth in North America', said Amit Gupta, President and CEO of Solido Design Automation.

Marcisz brings a proven track record of over 20 years experience in the EDA, semiconductor and software industries.

He has held senior sales positions at Viewlogic Systems (now Synopsys), Ambit Design Systems (now Cadence Design Systems), Arithmatica and Barcelona Design.

Earlier in his career Marcisz was Design Tools Application Manager at LSI Logic, where he led an engineering team responsible for field sales and applications product support for LSI's ASIC design tools.

He holds a BS in electrical engineering from the University of Hartford and an MBA from the University of Phoenix.

 

Suite speeds real-time Linux development

RTLinuxPro for Windows, from real-time Linux expert FSM Labs, allows any Windows workstation to be used to develop RTLinuxPro hard-real-time applications.

Available now from SDC, RTLinuxPro for Windows is an innovative Microsoft Windows-hosted cross-development product. RTLinuxPro for Windows, from real-time Linux expert FSM Labs, allows any Windows workstation to be used to develop RTLinuxPro hard-real-time applications. RTLinuxPro for Windows features a full graphical interface and build system based on the industry-standard Eclipse IDE.

'We waited to release a Windows-hosted tool kit until we could offer the same high level of reliability offered by our Linux hosted products', commented FSMLabs CTO Cort Dougan.

'RTLinuxPro for Windows features a solid graphical user interface, and unlike other Linux cross development kits for Windows, provides developers with the same tools that are tested and deployed with our Linux based development systems, leveraging years of quality assurance and support experience'.

Most prior attempts to support Embedded Linux development on Microsoft Windows rely on a fragile stack of marginally compatible software tools ported from Unix to Windows.

In contrast, FSMLabs innovative approach places its entire standard development environment on top of Windows.

Developers simply install and launch RTLinuxPro for Windows as a standard Windows application and can immediately take advantage of the Eclipse-based IDE to develop projects and automatically cross develop, load, execute and debug code on target devices.

The enterprise strength environment insulates programmers from differences between different Windows versions.

RTLinuxPro for Windows also offers a prebuilt and preconfigured network mountable Linux root file system that is transparently available to the target embedded device - and that can be moved to target device flash memory.

For developers who prefer command line interfaces and scripting capabilities, RTLinuxPro for Windows also provides a familiar command line interface and text editor.

'Our goal is to allow developers to be productive right away rather than spending time installing and configuring a development system', added Dougan.

Using FSMLabs' RTCore platform, developers can write hard real-time software to control motors, acquire data, and move network packets in real-time while also taking advantage of the enterprise software platform provided by Linux.

Linux provides sophisticated networking and storage capabilities, comprehensive security functionality, excellent driver support, and a wealth of applications, while RTCore provides a Posix API environment for hard real-time applications.

RTCore's patented virtualisation technology allows Linux to be run alongside real-time code while being prevented from interfering with timing.

RTLinuxPro for Windows is released as part of FSMLabs Embedded Enterprise initiative.

The initiative exploits the productive synergy between state of the art Posix real-time in FSMLabs RTCore and the sophisticated capabilities and rich base of drivers, middleware and applications available on the Linux and BSD clients and other interoperable systems.

The RTLinuxPro Cross Development system leverages the interoperability of Microsoft Windows, Eclipse, Java, Linux and Posix to improve programmer productivity.

Monday, November 20, 2006

 

Navigation environment for HDL designs

Re-using existing code (legacy or third party) is becoming everyday practice to get designs done within schedule.

On his way to a wedding party it starts to rain and Mike misses the first exit from the highway, the next exit seems to be a million miles away. When he finally gets there he needs to follow some unfamiliar routes and he gets lost in a city he doesn't know. After some hours of searching he finally reaches the party location.

Wet, down and tired he walks in a crowd of strangers, then he sees a familiar face.

It's Sam, one of his colleagues who just got in a meeting when Mike left the office this afternoon.

'Hi Sam, how did you get here so quickly?', he asks.

Sam explains that he's so satisfied with his new navigation system.

Ever since he's had it, he's been more relaxed when going somewhere and he doesn't have to worry about complex routes or bad signs along the road.

This is close to what many design engineers experience every day with their HDL.

Re-using existing code (legacy or third party) is becoming everyday practice to get designs done within schedule.

However it might take a lot of additional time if you need to find your way through unfamiliar code without any tools that tell you where to look for the things you're searching.

In most cases, you're left with a project that takes more time then your manager has put on the schedule and you'll have to fix it.

Many design engineers around the world already discovered the advantages of working with HDL Companion.

This is a high level analysis and navigation environment for HDL designs.

HDL Companion automatically extracts numerous design details from the code and represents them in an orderly fashion to the user.

Finding definitions, searching through the design hierarchy, looking for objects in packages or modules, it all becomes fun when you have the right tool on your desk.

HDL Companion not only provides the options that enable you to explore HDL designs quickly, but also adds many other features, like: revision control, documentation generation, linting, syntax checking, interfacing to many third-party tools and team based design support.

All these things together provide an environment that should be on every engineer's desktop.

Especially as HDL Companion can be used and put aside at any time.

It only uses your HDL design files which can be ordered in your preferred design structure.

This means that there's no specific design database that forces you to start and finish your design with this tool.

It's just like the navigation system in your car, it doesn't change the roads but it tells you how to get to your destination via the fastest route.

 

Schmidt to lead technology development

PrismTech has appointed distributed computing expert Dr Douglas C Schmidt as its Principal Technologist.

PrismTech has appointed distributed computing expert Dr Douglas C Schmidt as its Principal Technologist. Dr Schmidt is an internationally renowned and widely cited expert on distributed computing middleware, object-oriented patterns and frameworks, and distributed real-time and embedded (DRE) systems. He has authored eight best-selling books and over 300 papers in top IEEE, ACM, IFIP and USENIX technical journals, conferences, and books - and has also presented over 300 keynote addresses, invited talks, and tutorials - that cover a range of topics, including high-performance communication software systems, parallel processing for high-speed networking protocols, real-time distributed computing with CORBA, real-time Java technology, object-oriented patterns for concurrent and distributed systems, and model-driven engineering (MDE) tools.

Over the past two decades, Dr Schmidt has led the development of the ACE, which is a widely used open-source object-oriented framework that contains a rich set of components that implement patterns for high-performance DRE systems.

Dr Schmidt and the members of his research group in the Distributed Object Computing (DOC) Group at the Institute for Software Intensive Systems (ISIS) at Vanderbilt University have used ACE to develop a high performance, real-time CORBA ORB endsystem called the ACE ORB (TAO), which is open-source software that supports end-to-end quality-of-service assurance over high-speed networks and embedded interconnects.

In turn, ACE and TAO form the basis for the Component-Integrated ACE ORB (CIAO), which is a real-time open-source implementation of Lightweight CORBA Component Model (CCM) built by the DOC Group.

Most recently, the DOC Group has developed CoSMIC, which is a collection of open-source domain-specific modelling languages and their associated MDE analysis/synthesis tools that support various phases of DRE system development, analysis, configuration, and deployment.

ACE, TAO, CIAO, and CoSMIC have been used successfully by thousands of developers at hundreds of companies world-wide.

In collaboration with his colleagues, Dr Schmidt has applied these middleware platforms and MDE tools on large-scale projects at many companies, including BBN Technologies, Boeing, Cisco, Ericsson, Kodak, Lockheed Martin, Lucent, Motorola, Nokia, Nortel, Raytheon, Qualcomm, SAIC, Siemens, Sprint, and Telcordia.

These projects involve telecommunications systems, medical imaging systems, real-time avionic systems, shipboard computing systems, and distributed interactive simulation systems.

In addition to serving as Principal Technologist at PrismTech, Dr Schmidt is a Full Professor of Computer Science, the Associate Chair of Computer Science and Engineering, and a Senior Researcher at the Institute for Software Integrated Systems (ISIS), all at Vanderbilt University.

He previously served as a Program Manager and Scientific and Engineering Technical Assistant in the DARPA Information eXploitation Office (IXO), where he led the US national effort on QoS-enabled component middleware and MDE tool research in the Program Composition for Embedded Systems (PCES) and Adaptive and Reflective Middleware Systems (ARMS) programs.

He also served as the Deputy Director of the DARPA Information Technology Office (ITO), where he helped to set the US national IT R and D agenda on autonomous systems, network-centric command and control systems, distributed real-time and embedded systems, and augmented cognition.

In addition, Dr Schmidt served as the co-chair for the Software Design and Productivity (SDP) co-ordinating Group of the Federal government's multi-agency Information Technology Research and Development (IT R and D) Program, the collaborative IT research effort of the major US science and technology agencies.

'Doug is a true visionary in distributed computing and model-driven engineering and I'm delighted that he has chosen to join PrismTech', said Keith Steele, CEO of PrismTech.

'I'm very excited at the prospect of joining PrismTech', said Dr Schmidt.

Sunday, November 19, 2006

 

New-generation compiler takes half the time

Progate Group Corp has successfully taped out an advanced mobile communications chip using the Synopsys IC Compiler next-generation place-and-route solution.

Progate Group Corporation (PGC), one of the largest SoC/ASIC design service providers in Taiwan, has successfully taped out an advanced mobile communications chip using the Synopsys IC Compiler next-generation place-and-route solution. By utilising the new optimisations in the IC Compiler tool, PGC designers were not only able to reduce the die size but also complete the design ahead of schedule. 'When it comes to mobile communications IC products, low unit cost and fast time to market are most critical to product success', said Albert Hu, CEO of PGC.

'Thanks to the excellent implementation design technology and services from Synopsys, we were able to shrink the die size by 10% while completing the design within just one and a half months'.

For this 1.5-million-gate, 130nm design, PGC used Synopsys' IC Compiler solution to meet tight timing and performance goals.

PGC also saw improvement in turnaround time consistent with other IC Compiler users who have reported 2x faster turnaround time compared with the previous-generation Physical Compiler/Astro solution, on average.

Much of this productivity boost can be attributed to IC Compiler's Extended Physical Synthesis (XPS) technology that unifies optimisations across synthesis, placement, clock tree and routing.

In addition, PGC benefited from tighter correlation to Synopsys' golden Star-RCXT extraction tool and PrimeTime sign-off technologies to accelerate the overall time to design closure.

A long-time user of Synopsys physical implementation products, PGC is actively deploying IC Compiler into production for additional customer designs.

'The successful tapeout by PGC, including the very impressive reduction in die size, speaks to the strength of the IC Compiler solution', said Antun Domic, Senior Vice President and General Manager of Synopsys' Implementation Group.

'As PGC ramps up on their 90nm designs, they can expect to benefit from the full complement of the technology innovations in IC Compiler, resulting in higher design performance and improved designer productivity'.

IC Compiler is Synopsys' next-generation place-and-route solution.

It provides superior results and faster time-to-results by extending physical synthesis to full place-and-route, and by enabling signoff-driven design closure.

Current-generation solutions have a limited horizon because placement, clock tree and routing are separate, disjointed operations.

IC Compiler's Extended Physical Synthesis (XPS) technology breaks down the walls between these steps by extending physical synthesis to full place-and-route.

IC Compiler has a unified, TCL-based architecture that implements innovations and harnesses some of the best Synopsys core technologies.

It is a complete place-and-route system with everything necessary to do next-generation designs, including physical synthesis, placement, routing, timing, signal integrity (SI) optimisation, power reduction, design-for-test (DFT) and yield optimisation.

 

IBM signs up for 65nm ASIC support

Cadence Design Systems has signed an agreement to incorporate Encounter RTL Compiler global synthesis and Encounter Test technologies into the IBM 65nm ASIC design kit.

Cadence Design Systems has signed an agreement to incorporate Encounter RTL compiler global synthesis and Encounter Test technologies into the IBM 65nm ASIC design kit. This new kit provides IBM's ASIC customers with an optimised path for automated test solutions and test logic-design processing at 65nm. The companies will co-operatively support customers using the ASIC kit.

The collaboration offers IBM's ASIC customers a proven way to address logic-design challenges before handoff to IBM, accelerating the completion of higher quality designs.

ASIC customers will gain access to Cadence Test and Synthesis technologies when they receive the 65nm IBM ASIC design kit.

'For nearly two years, IBM has worked closely with Cadence to ensure that our ASIC clients continue to benefit from a differentiated test methodology that helps reduce their test development resources by implementing automated test pattern generation and diagnosis', said Rich Busch, Director, ASIC Products Business Unit, IBM Technology Collaboration Solutions.

'This has been accomplished by using Cadence synthesis and test technologies which are key components of our methodology to deliver industry leading shipped-product quality level (SPQL)'.

'We are delighted about the outcome of this effort with IBM and the benefits our ASIC customers will gain', said Jim Miller, Executive Vice President, Products and Technologies Organisation.

'The new design kit, leveraging Cadence technologies, will enable ASIC customers to complete 65nm ASIC designs more predictably and with fewer iterations'.

 

Italian developers adopt SDR tools

Selex Communications will use PrismTech's Spectra Tools for the development and deployment of its software-defined radio product line.

Selex Communications, a Finmeccanica company, is to use PrismTech's Spectra Tools for the development and deployment of its software-defined radio (SDR) product line. Selex Communications is involved in the Italian programme for SDR and also participates in international SDR programmes such as MIDS and JTRS. The company's R and D activities on SDR began in 2002 when a program funded by the Italian Ministry of Defence and Selex Communications was established with the aim to develop an SDR family of products that would replace existing radios and run legacy and future waveforms.

Loris Schettino, Defence Communications Marketing Manager at Selex Communications commented: 'Selex Communications is committed to the development of the full family of software-defined radio, both hardware and software, for aeronautical, naval, fixed and tactical platforms'.

'What we were looking for, in relation to the functional components, was a solution that would allow our company to reduce the development time for single platforms'.

'PrismTech's Spectra Tools was the solution that could best satisfy our requirements'.

Dominick Paniscotti, VP of SDR Products at PrismTech commented: 'We are extremely proud to have Selex Communications join the Spectra user community'.

'PrismTech is working with a large number of SDR OEMs, programs and system integrators around the world and is receiving consistent praise for the ease of use, productivity gains and flexibility of the Spectra Tools'.

'We look forward to a long and very successful relationship with Selex by providing superior SDR tools and infrastructure to support the rapid development and deployment of Selex' SDR programmes'.

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