Friday, July 21, 2006
FPGA design environment adds IP generation support
The latest version of the Actel Libero integrated design environment has new features intended to increase the flexibility, efficiency and performance of designs based on the company's FPGAs.
Actel has released a new version of its Libero integrated design environment (IDE) with new features intended to increase the flexibility, efficiency and performance of designs based on the company's field-programmable gate arrays (FPGAs). With the enhanced SmartGen, SmartTime and SmartPower tools, the Libero IDE 7.2 offers new capabilities for intellectual property (IP) generation to support the Actel Fusion Programmable System Chip (PSC) offerings. It also offers advanced timing and power analysis functionalities for designers using the Actel Fusion, ProASIC3 and RTAX-S families.
'As more system engineers turn to FPGAs, the Libero IDE 7.2 allows these designers to leverage the capabilities of the Fusion platform whether they are coming from an SoC, mixed-signal, discrete or analogue design environment', said Jake Chuang, Senior Director, Application Solutions Marketing at Actel.
'Delivering on Actel's commitment to deliver tools to increase designer efficiency and FPGA device performance, the comprehensive IDE, with its new SmartGen, SmartTime and SmartPower features, now also enables designers to meet their design requirements while lowering costs and improving the reliability of their complete system'.
For a large variety of commonly used IP functions, the SmartGen tool provides users with design automation functionality to import existing cores and create new ones for their Fusion-based designs.
New features include a sample sequencer, a sample sequence configurator and a visual phase-locked loop (PLL) configurator.
Further, the state management capability that audits module changes and dependencies can now pass this information directly to Libero, allowing the designer to update all dependent modules with one click.
In addition, SmartGen now supports the direct update of nonvolatile memory for analogue system blocks, thereby reducing or eliminating lengthy iterations through synthesis.
Actel's SmartTime feature provides static timing analysis capabilities based on industry standards, such as Synopsys Design Constraints (SDC), as well as new visual constraint dialogs, thereby easing the transition from ASICs to mixed-signal FPGAs.
Clock-source latency analysis, which allows the definition of a clock constraint for clock jitter, is another new feature to help designers analyse FPGA timing in the context of its surrounding environment.
SmartTime also supports recovery and removal checks for proper timing of asynchronous signals for both internally and externally generated clocks.
Enhancements to Actel's SmartPower power analysis tool, enables users to perform detailed power-consumption analysis, helping to conserve power, cut costs and improve design reliability.
SmartPower is now able to generate power consumption information for nets, gates, I/O, RAM, FIFOs and clocks or alternatively, block-by-block by component type.
The tool performs rail checks and collates power for all defined voltages.
Further, SmartPower supports an enable-rate specifier capability for the per-load estimation of time and active output drives, offering designers the ability to achieve more accurate system power calculations.
Actel has released a new version of its Libero integrated design environment (IDE) with new features intended to increase the flexibility, efficiency and performance of designs based on the company's field-programmable gate arrays (FPGAs). With the enhanced SmartGen, SmartTime and SmartPower tools, the Libero IDE 7.2 offers new capabilities for intellectual property (IP) generation to support the Actel Fusion Programmable System Chip (PSC) offerings. It also offers advanced timing and power analysis functionalities for designers using the Actel Fusion, ProASIC3 and RTAX-S families.
'As more system engineers turn to FPGAs, the Libero IDE 7.2 allows these designers to leverage the capabilities of the Fusion platform whether they are coming from an SoC, mixed-signal, discrete or analogue design environment', said Jake Chuang, Senior Director, Application Solutions Marketing at Actel.
'Delivering on Actel's commitment to deliver tools to increase designer efficiency and FPGA device performance, the comprehensive IDE, with its new SmartGen, SmartTime and SmartPower features, now also enables designers to meet their design requirements while lowering costs and improving the reliability of their complete system'.
For a large variety of commonly used IP functions, the SmartGen tool provides users with design automation functionality to import existing cores and create new ones for their Fusion-based designs.
New features include a sample sequencer, a sample sequence configurator and a visual phase-locked loop (PLL) configurator.
Further, the state management capability that audits module changes and dependencies can now pass this information directly to Libero, allowing the designer to update all dependent modules with one click.
In addition, SmartGen now supports the direct update of nonvolatile memory for analogue system blocks, thereby reducing or eliminating lengthy iterations through synthesis.
Actel's SmartTime feature provides static timing analysis capabilities based on industry standards, such as Synopsys Design Constraints (SDC), as well as new visual constraint dialogs, thereby easing the transition from ASICs to mixed-signal FPGAs.
Clock-source latency analysis, which allows the definition of a clock constraint for clock jitter, is another new feature to help designers analyse FPGA timing in the context of its surrounding environment.
SmartTime also supports recovery and removal checks for proper timing of asynchronous signals for both internally and externally generated clocks.
Enhancements to Actel's SmartPower power analysis tool, enables users to perform detailed power-consumption analysis, helping to conserve power, cut costs and improve design reliability.
SmartPower is now able to generate power consumption information for nets, gates, I/O, RAM, FIFOs and clocks or alternatively, block-by-block by component type.
The tool performs rail checks and collates power for all defined voltages.
Further, SmartPower supports an enable-rate specifier capability for the per-load estimation of time and active output drives, offering designers the ability to achieve more accurate system power calculations.
# posted by Swathi @ 1:56 AM 
