Wednesday, November 22, 2006
Wireless SoC reference flow bears fruit
Cadence Design Systems and UMC have announced the success of their RF integrated-circuit design and verification on a codeveloped wireless system-on-chip (SoC) reference flow.
Cadence Design Systems and leading global semiconductor foundry UMC have announced the success of their RF integrated-circuit design and verification on a codeveloped wireless system-on-chip (SoC) reference flow. The flow, featuring the Cadence QRC Extraction and the Virtuoso UltraSim Full-chip Simulator, combines the Cadence Virtuoso custom design platform and UMC's RFCMOS process to deliver silicon-accurate chip simulation and verification flows. UMC and Cadence announced their alliance to streamline wireless design for the fabless market on 6th October 2005.
Since then, UMC has successfully produced a test chip that verifies the Cadence QRC Extraction technology.
The Cadence Virtuoso UltraSim provided UMC with transistor-level transceiver simulation, which reduced the verification cycle time by half.
UMC and Cadence worked closely together to develop a methodology and flow to verify post-layout transistor-level full-chip transceivers, by combining UMC's 0.13um MM/RF PDK validated for the Virtuoso platform, silicon-accurate Cadence QRC Extraction technology, and the Virtuoso UltraSim.
'Designers building SoCs for wireless applications can gain a competitive advantage when they use Virtuoso combined with UMC's RFCMOS process', said Patrick Lin, Chief SoC Architect at UMC.
'For back annotation verification, Cadence QRC Extraction provides a convenient and accurate methodology to predict the performance in critical building blocks such as LC-tank VCO.
Further, the extraction that covers RLCK can be used to predict with greater accuracy the frequencies and how the design will perform in silicon'.
'These benefits and our alliance with Cadence have resulted in a seamless design environment for the analogue/RF design communities'.
The continually increasing demand for feature-rich wireless devices with complex functionality and minimised area and power requirements is driving the need for silicon-accurate parasitic extraction and transistor-level full-chip simulation flows that reduce risk and time to market for custom wireless SoCs.
'Cadence and UMC are working side-by-side to drive and deliver integrated, low-cost, high-performance, low-power wireless SoC solutions to our mutual customers', said Charles Giorgetti, Corporate Vice-President, Product Marketing, at Cadence.
'By collaborating with UMC, we are able to provide a silicon-validated methodology that meets changing requirements for wireless designers as they develop new and increasingly more innovative products'.
Cadence Design Systems and leading global semiconductor foundry UMC have announced the success of their RF integrated-circuit design and verification on a codeveloped wireless system-on-chip (SoC) reference flow. The flow, featuring the Cadence QRC Extraction and the Virtuoso UltraSim Full-chip Simulator, combines the Cadence Virtuoso custom design platform and UMC's RFCMOS process to deliver silicon-accurate chip simulation and verification flows. UMC and Cadence announced their alliance to streamline wireless design for the fabless market on 6th October 2005.
Since then, UMC has successfully produced a test chip that verifies the Cadence QRC Extraction technology.
The Cadence Virtuoso UltraSim provided UMC with transistor-level transceiver simulation, which reduced the verification cycle time by half.
UMC and Cadence worked closely together to develop a methodology and flow to verify post-layout transistor-level full-chip transceivers, by combining UMC's 0.13um MM/RF PDK validated for the Virtuoso platform, silicon-accurate Cadence QRC Extraction technology, and the Virtuoso UltraSim.
'Designers building SoCs for wireless applications can gain a competitive advantage when they use Virtuoso combined with UMC's RFCMOS process', said Patrick Lin, Chief SoC Architect at UMC.
'For back annotation verification, Cadence QRC Extraction provides a convenient and accurate methodology to predict the performance in critical building blocks such as LC-tank VCO.
Further, the extraction that covers RLCK can be used to predict with greater accuracy the frequencies and how the design will perform in silicon'.
'These benefits and our alliance with Cadence have resulted in a seamless design environment for the analogue/RF design communities'.
The continually increasing demand for feature-rich wireless devices with complex functionality and minimised area and power requirements is driving the need for silicon-accurate parasitic extraction and transistor-level full-chip simulation flows that reduce risk and time to market for custom wireless SoCs.
'Cadence and UMC are working side-by-side to drive and deliver integrated, low-cost, high-performance, low-power wireless SoC solutions to our mutual customers', said Charles Giorgetti, Corporate Vice-President, Product Marketing, at Cadence.
'By collaborating with UMC, we are able to provide a silicon-validated methodology that meets changing requirements for wireless designers as they develop new and increasingly more innovative products'.
# posted by Swathi @ 10:33 AM 
