Thursday, February 08, 2007
Bit-error-rate tester takes DesignVision Award
Agilent Technologies has won a 2007 DesignVision Award in the test and measurement category for its J-BERT N4903A.
Agilent Technologies has won a 2007 DesignVision Award in the test and measurement category for its J-BERT N4903A, a high-performance serial bit-error-rate tester with an industry-first built-in, compliant and tunable clock data recovery (CDR). The International Engineering Consortium (IEC), which presents the DesignVision Awards, acknowledges individuals and companies that offer innovative and unique applications, products, technologies and services of impact to the semiconductor industry. IEC President John Janowiak commented: 'Our DesignVision Awards honour those catalyzing positive change in high-technology, business and academia, completely in line with the IEC's mission'.
'We are delighted to recognise the DesignVision finalists and share the best design advancements and innovators with the entire industry'.
The J-BERT N4903A is the only complete jitter tolerance test solution.
It provides integrated and calibrated jitter sources for stressed eye testing of gigabit receivers.
The new compliant and tunable CDR is also integrated into the J-BERT box.
This enables engineers in characterisation and validation labs to get precise jitter budget results for clock-less devices.
Engineers save test setup time by using J-BERT's new library of compliant CDR settings for many popular standards, such as PCI Express, Serial Advanced Technology Attachment (SATA), Fibre Channel, fully buffered DIMM, Common Electrical interface (CEI), 10Gbit/s Ethernet and XFP/XFI.
'We are pleased to be honoured by the IEC for the J-BERT N4903A with CDR', said Sigi Gross, Vice President and General Manager of Agilent's Digital Verification Solutions Division.
Agilent Technologies has won a 2007 DesignVision Award in the test and measurement category for its J-BERT N4903A, a high-performance serial bit-error-rate tester with an industry-first built-in, compliant and tunable clock data recovery (CDR). The International Engineering Consortium (IEC), which presents the DesignVision Awards, acknowledges individuals and companies that offer innovative and unique applications, products, technologies and services of impact to the semiconductor industry. IEC President John Janowiak commented: 'Our DesignVision Awards honour those catalyzing positive change in high-technology, business and academia, completely in line with the IEC's mission'.
'We are delighted to recognise the DesignVision finalists and share the best design advancements and innovators with the entire industry'.
The J-BERT N4903A is the only complete jitter tolerance test solution.
It provides integrated and calibrated jitter sources for stressed eye testing of gigabit receivers.
The new compliant and tunable CDR is also integrated into the J-BERT box.
This enables engineers in characterisation and validation labs to get precise jitter budget results for clock-less devices.
Engineers save test setup time by using J-BERT's new library of compliant CDR settings for many popular standards, such as PCI Express, Serial Advanced Technology Attachment (SATA), Fibre Channel, fully buffered DIMM, Common Electrical interface (CEI), 10Gbit/s Ethernet and XFP/XFI.
'We are pleased to be honoured by the IEC for the J-BERT N4903A with CDR', said Sigi Gross, Vice President and General Manager of Agilent's Digital Verification Solutions Division.
# posted by Swathi @ 8:45 PM 
